Saturday, July 29, 2006

NYTimes on Intel's Core 2 Duo

The write-up by the New York Times contained the sentence: The Core 2 Duo, Intel says, can deliver as much as 40 percent better performance while using as much as 40 percent less power and giving off less heat.

The Times also noted:

The chief executive of Intel, Paul S. Otellini, told an audience gathered at the company’s headquarters here that the chips represented the most significant advancement in computer chip design and performance since the Pentium processor in 1993.


The Core 2 Duo also arrives just as Intel is completing a review of its operations in hopes of becoming more efficient. Mr. Otellini declined to reveal whether the company, which earlier this month announced it would lay off 1,000 managers, would have additional job cuts.

Rupert Goodwins of ZDNet gives more details:

It is hard to overstate the importance of the Core micro-architecture to Intel, and thus to the rest of the industry. The product of a major debate within Intel (what Pat Gelsinger, General Manager of the Digital Enterprise Group, called the 'speed freaks versus brainiacs'), it marks the victory of those who felt that extra performance was best achieved not by constantly upping the processor's clock speed, but by going for ever more parallel systems with much finer control of performance versus power consumption.


All of the above is true separately for each core, each of which operates entirely independently of the other. They share their Level 2 cache, though, and this is where Intel has optimised operations for the simultaneous use of both cores. This means that when both cores are operating on the same area of memory, just one copy of the data is needed in the cache, increasing efficiency and leaving more cache for other processes. The cache also dynamically allocates how much is used by each core, so that if one is idle or operating in a slow, low-power mode, more cache is available to the other.


Underlying all this is Intel's dynamic power management. Areas of the chip that aren't needed at any particular point can be disconnected from main power, while others are switched into low-power modes when they don't need to deliver full performance. This extends to buses, which can be split so that parts not needed are powered down without affecting the rest, and the cache, which puts parts of itself into low-power modes that maintain their contents but react only sluggishly when this wouldn't affect performance.


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